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1 pin configuration plcc 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 [a7] gpi1 [a6] gpi0 [a5] wp [a4] tbl [a3] id3 [a2] id2 [a1] id1 [a0] id0 [i/o0] lad0 ic (v il ) [ic(v ih )] ce [nc] nc nc vcc [vcc] init [oe] lframe [we] rfu [ry/by] rfu [i/o7] 4 3 2 1 32 31 30 14 15 16 17 18 19 20 [i/o1] lad1 [i/o2] lad2 [gnd] gnd [i/o3] lad3 [i/o4] rfu [i/o5] rfu [i/o6] rfu gpi2 [a8] gpi3 [a9] rst [rst] vpp [vpp] vcc [vcc] clk [r/c] gpi4 [a10] [ ] designates a/a mux mode features ? conforms to intel lpc interface specification 1.0 4m bits of flash memory for platform code/data storage ? automated byte-program and sector-erase operations two configurable interfaces ? low pin count (lpc) interface for in-system operation ? address/address multiplexed (a/a mux) interface for programming during manufacturing low pin count hardware interface mode ? 5-signal communication interface supporting x8 reads and writes ? read and write protection for each sector using software-controlled registers ? two hardware write-protect pins: one for the top boot sector, one for all other sectors ? five general-purpose inputs, gpis, for platform design flexibility ? operates with 33 mhz pci clock and 3.3v i/o address/address multiplexed (a/a mux) interface ? 11-pin multiplexed address and 8-pin data interface power supply specifications ?v cc : 3.3v 0.3v industry-standard package ? 40-lead tsop or 32-lead plcc description the at49ll040 is a flash memory device designed to interface with the lpc bus for pc applications. a feature of the at49ll040 is the nonvolatile memory core. the high-performance memory is arranged in eleven sectors (see page 10). the at49ll040 supports two hardware interfaces: low pin count (lpc) for in-system operation and address/address multiplexed (a/a mux) for programming during manu- facturing. the ic (interface configuration) pin of the device provides the control between the interfaces. the interface mode needs to be selected prior to power-up or before return from reset (rst or init low to high transition). an internal command user interface (cui) serves as the control center between the two device interfaces (lpc and a/a mux) and internal operation of the nonvolatile memory. a valid command sequence written to the cui initiates device automation. 4-megabit low-pin count flash memory at49ll040 rev. 3343a?flash?6/03 tsop, type i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (nc) ce [ic (v ih )] ic (v il ) [nc] nc [nc] nc [nc] nc [nc] nc [a10] gpi4 [nc] nc [r/c] clk [vcc] vcc [vpp] vpp [rst] rst [nc] nc [nc] nc [a9] gpi3 [a8] gpi2 [a7] gpi1 [a6] gpi0 [a5] wp [a4] tbl gnda [gnda] vcca [vcca] lframe [we] init [oe] rfu [ry/by] rfu [i/o7] rfu [i/o6] rfu [i/o5] rfu [i/o4] vcc [vcc] gnd [gnd] gnd [gnd] lad3 [i/o3] lad2 [i/o2] lad1 [i/o1] lad0 [i/o0] id0 [a0] id1 [a1] id2 [a2] id3 [a3] [ ] designates a/a mux mode
2 at49ll040 3343a?flash?6/03 the vpp pin gives complete data protection when v pp < v pplk . v cc and v pp can be tied together for a simple, low-power 3v design. programming board solutions should design such that v pp draws from the same supply as v cc , and should assume that full program- ming current may be drawn from either pin. low pin count interface the low pin count (lpc) interface is designed to work with the i/o controller hub (ich) during platform operation. the lpc interface consists primarily of a five-signal communication interface used to control the operation of the device in a system environment. the buffers for this inter- face are pci compliant. to ensure the effective delivery of security and manageability features, the lpc interface is the only way to get access to the full feature set of the device. the lpc interface is equipped to operate at 33 mhz, synchronous with the pci bus. address/address multiplexed interface the a/a mux interface is designed as a programming interface for oems to use during motherboard manufacturing or component pre-programming. the a/a mux refers to the multiplexed row and column addresses in this interface. this approach is required so that the device c an be tested and programmed quickly with automated test equipment (ate) and prom programmers in the oem?s manufacturing flow. this interface also allows the device to have an efficient programming interface with potentially large future densities, while still fitting into a 32-pin package. only basic reads, programming, and erase of the nonvolatile memory sectors can be performed through the a/a mux interface. in this mode lpc features, security features and regis- ters are unavailable. a row/column (r/c ) pin determines which set of addresses ?rows or columns? are latched. block diagram lpc interface a10 - a0 i/o7 - i/o0 flash array control logic a/a mux interface rst ic clk lad (3:0) lframe id (3:0) gpi (4:0) tbl ce wp we ry/by r/c oe init
3 at49ll040 3343a?flash?6/03 pin description table 1 details the usage of each of the device pins. most of the pins have dual function- ality, with functions in both the firmware hub and a/a mux interfaces. a/a mux functionality for pins is shown in bold in the description box for that pin. all pins are designed to be compliant with voltage of v cc + 0.3v max, unless otherwise noted. table 1. pin description symbol type interface name and function lpc a/a mux ic input x x interface configuration pin: this pin determines which interface is operational. this pin is held high to enable the a/a mux interface. this pin is held low to enable the lpc interface. this pin must be set at power-up or before return from reset and not changed during device operation. this pin is pulled down with an internal resistor, with values between 20 and 100 k ? . with ic high (a/a mux mode), this pin will exhibit a leakage current of approximately 200 a. this pin may be floated, which will select lpc mode. rst input x x interface reset: valid for both a/a mux and lpc interface operations. when driven low, rst inhibits write operations to provide data protection during power transitions, resets internal automation, and tri-states pins lad[3:0] (in lpc interface mode). rst high enables normal operation. when exiting from reset, the device defaults to read array mode. init input x processor reset: this is a second reset pin for in-system use. this pin is internally combined with the rst pin. if this pin or rst is driven low, identical operation is exhibited. this signal is designed to be connected to the chipset init signal (max voltage depends on the processor. do not use 3.3v.) a/a mux = oe clk input x 33 mhz clock for lpc interface: this input is the same as the pci clock and adheres to the pci specification. a/a mux = r/c lad[3:0] i/o x address and data: these pins provide lpc control signals, as well as addresses and command inputs/outputs data. a/a mux = i/o[3:0] lframe input x frame: this pin indicates the start of a data transfer operation; also used to abort an lpc cycle in progress. a/a mux = we id[3:0] input x identification inputs: these four pins are part of the mechanism that allows multiple parts to be attached to the same bus. the strapping of these pins is used to identify the component. the boot device must have id[3:0] = 0000, and it is recommended that all subsequent devices should use a sequential up-count strapping (i.e., 0001, 0010, 0011, etc.). these pins are pulled down with internal resistors, with values between 20 and 100 k ? when in lpc mode. any id pins that are pulled high will exhibit a leakage current of approximately 200 a. any pins intended to be low may be left to float. in a single lpc system, all may be left floating. a/a mux = a[3:0]
4 at49ll040 3343a?flash?6/03 ce input x when ce is low, the device is enabled. this pin is pulled down with an internal resistor and can exhibit a leakage current of approximately 10 a. since this pin is internally pulled down and thus can be left unconnected, the at49ll040 is compatible with systems that do not use a ce signal. to reduce power, the device is placed in a low-power standby mode when ce is high. gpi[4:0] input x general purpose inputs: these individual inputs can be used for additional board flexibility. the state of these pins can be read through lpc registers. these inputs should be at their desired state before the start of the pci clock cycle during which the read is attempted, and should remain at the same level until the end of the read cycle. they may only be used for 3.3v signals. unused gpi pins must not be floated. a/a mux = a[10:6] tbl input x top sector lock: when low, prevents programming or sector erase to the highest addressable sector (10) regardless of the state of the lock registers tbl high disables hardware write protection for the top sector, though register- based protection still applies. the status of tbl does not affect the status of sector-locking registers. a/a mux = a4 wp input x write-protect: when low, prevents programming or sector erase to all but the highest addressable sectors (0 - 9), regardless of the state of the corresponding lock registers. wp -high disables hardware write protection for these sectors, though register-based protection still applies. the status of tbl does not affect the status of sector-locking registers. a/a mux = a5 a0 - a10 input x low-order address inputs: inputs for low-order addresses during read and write operations. addresses are internally latched during a write cycle. for the a/a mux interface these addresses are latched by r/c and share the same pins as the high-order address inputs. i/o0 - i/o7 i/o x data input/outputs: these pins receive data and commands during write cycles and transmit data during memory array and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. oe input x output enable: gates the device?s outputs during a read cycle. r/c input x row-column address select: for the a/a mux interface, this pin determines whether the address pins are pointing to the row addresses, a0 - a10, or to the column addresses a11 - a18. we input x write enable: controls writes to the array sectors. addresses and data are latched on the rising edge of the we pulse. v pp supply x x sector erase/program power supply: the vpp pin can be left unconnected. sector erase or program with an invalid v pp (see dc characteristics) produces spurious results and should not be attempted. table 1. pin description (continued) symbol type interface name and function lpc a/a mux
5 at49ll040 3343a?flash?6/03 low pin count interface (lpc) table 2 lists the seven required signals used for the lpc interface. lad[3:0]: the lad[3:0] signal lines communica te address, control, and data informa- tion over the lpc bus between a master and a peripheral. the information communicated are: start, stop (abort a cycle), transfer type (memory, i/o, dma), trans- fer direction (read/write), address, data, wait states, dma channel, and bus master grant. lframe : lframe is used by the master to indicate the start of cycles and the termina- tion of cycles due to an abort or time-out condition. this signal is to be used be by peripherals to know when to monitor the bus for a cycle. v cc supply x x device power supply: internal detection automatically configures the device for optimized read performance. do no float any power pins. with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltages (see dc characteristics) produce spurious results and should not be attempted. gnd supply x x ground: do not float any ground pins. v cca supply x x analog power supply: this supply should share the same system supply as v cc . gnda supply x x analog ground: should be tied to same plane as gnd. rfu x reserved for future use: these pins are reserved for future generations of this product and should be connected accordingly. these pins may be left disconnected or driven. if they are driven, the voltage levels should meet v ih and v il requirements. a/a mux = i/o[7:4] nc x x no connect: pin may be driven or floated. if it is driven, the voltage levels should meet v ih and v il . ry/by output x ready/busy: valid only in a/a mux mode. this output pin is a reflection of bit 7 in the status register. this pin is used to determine sector erase or program completion. table 1. pin description (continued) symbol type interface name and function lpc a/a mux table 2. lpc required signal list signal direction description peripheral master lad[3:0] i/o i/o multiplexed command, address and data lframe i o indicates start of a new cycle, termination of broken cycle. rst i i reset: same as pci reset on the master. the master does not need this signal if it already has pcirst on its interface. clk i i clock: same 33 mhz clock as pci clock on the master. same clock phase with typical pci skew. the master does not need this signal if it already has pciclk on its interface.
6 at49ll040 3343a?flash?6/03 the lframe signal is used as a general notificat ion that the lad[3:0] lines contain information relative to the start or stop of a cycle, and that peripherals must monitor the bus to determine whether the cycle is intended for them. the benefit to peripherals of lframe is, it allows them to enter lower power states internally. when peripherals sample lframe active, they are to immediately stop driving the lad[3:0] signal lines on the next clock and monitor the bus for new cycle information. reset: rst or init at vil initiates a device reset. in read mode, rst or init low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. rst or init must be held low for time t plph (a/a mux and lpc opera- tion). the lpc resets to read array mode upon return from reset, and all sectors are set to default (locked) status regardless of their locked state prior to reset. driving rst or init low resets the device, which resets the sector lock registers to their default (write-locked) condition. a reset time (t phqv a/a mux) is required from rst or init switching high until outputs are valid. likewise, the device has a wake time (t phrh a/a mux) from rst or init high until writes to the cui are recognized. a reset latency will occur if a reset procedure is performed during a programming or erase operation. during sector erase or program, driving rst or init low will abort the operation under- way, in addition to causing a reset latency. memory contents being altered are no longer valid, since the data may be partially erased or programmed. it is important to assert rst or init during system reset. when the system comes out of reset, it will expect to read from the memory array of the device. if a system reset occurs with no lpc reset (this will be hardware dependent), it is possible that proper cpu ini- tialization will not occur (the lpc memory may be providing status information instead of memory array data). cycle types: there are two types of cycles that are supported by the at49ll040: lpc memory read and lpc memory write. device operation read: read operations consist of start, cyctype + dir, address, tar, sync and data fields as shown in figure 1 and desc ribed in table 5. the different fields are described below. commands using the read mode include the following functions: read- ing memory from the array, reading the identifier codes, reading the lock bit registers and reading the gpi registers. memory information, identifier codes, or the gpi registers can be read independent of the v pp voltage. upon initial device power-up or after exit from reset mode, the device automatically resets to read array mode. read cycle, single byte: for read cycles, after the address is transferred, the master drives a tar field to give ownership of the bus to the lpc. after the second clock of the tar phase the lpc assumes the bus and begins driving sync values. when it is ready, it drives the low nibble, then the high nibble of data, followed by a tar field to give control back to the master. figure 1 shows a device that requires three sync clocks to access data. since the access time can begin once the address phase has been completed, the two clocks of the tar phase can be considered as part of the access time of the part. for example, a device with a 120 ns access time could as sert ?0101b? for clocks 1 and 2 of the sync phase and ?0000b? for the last clock of the sync phase. this would be equivalent to five clocks worth of access time if the device started that access at the conclusion of the preamble phase. once sync is achieved, the device then returns the data in two clocks and gives ownership of the bus back to the master with a tar phase.
7 at49ll040 3343a?flash?6/03 start: this one-clock field indicates the start of a cycle. it is valid on the last clock that lframe is sampled low. on the rising edge of clk with lframe low, the contents of lad3 - lad0 must be 0000b to indicate the start of a lpc cycle. cyctypes + dir: this one-clock field is used to indicate the type of cycle and direc- tion of transfer. bits 3 - 2 must be ?01b? for a memory cycle. bit 1 indicates the type of transfer: ?0? for read operation, ?1? for write operation. dir field indication of transfer: ?0? for read, ?1? for write. bit 0 is reserved. ?010xb? indicates a memory read cycle; while ?011xb? indicates a memory write cycle. maddr (memory address): this is an eight-clock field, which gives a 32-bit mem- ory address. lpc supports the 32-bit address protocol. the address is transferred with the most significant nibble first. address bit 23 directs reads and writes to memory locations (a 23 = 1) or to register access locations (a 23 = 0), address bits a 22 - a 19 are device id strapping bits, and a 18 - a 0 are decoded as memory addresses. turn-around (tar): this field is two clocks wide, and is driven by the master when it is turning control over to the lpc, (for example, to read data), and is driven by the lpc when it is turning control back over to the master. on the first clock of this two-clock- wide field, the master or lpc drives the lad[3:0] lines to ?1111b?. on the second clock of this field, the master or peripheral tri-states the lad[3:0] lines. sync: this field is used to add wait states. it can be several clocks in length. on target or dma cycles, this field is driven by the lpc. if the lpc needs to assert wait states, it does so by driving ?0101b? (short sync) on lad[3:0] until it is ready. when ready, it will drive ?0000b?. valid values for this field are shown in table 4. table 3. cyctype + dir fields lad[3:0] indication 010xb lpc memory read 011xb lpc memory write table 4. valid sync values bits[3:0] indication 0000 ready: sync achieved with no error. 0101 short wait: part indicating wait states.
8 at49ll040 3343a?flash?6/03 figure 1. lpc read waveforms note: 1. field contents are valid on the rising edge of the present clock cycle. cyctype + dir addr tar sync(3) tar data clk lframe lad[3:0] start 1 2 3 4 5 6 7 8 9 10111213141516 171819 table 5. lpc read cycle clock cycle field name field contents (1) lad[3:0] lad[3:0] direction comments 1 start 0000b in lframe must be active (low) for the part to respond. only the last start field (before lframe transitioning high) should be recognized. the start field contents indicate an lpc memory read cycle. 2 cyctype + dir 010xb in cycle type: indicates the type of cycle. bits 3:2 must be 01 for a memory cycle. dir: bit 1 indicates the direction of the transfer (0 for read). bit 0 is reserved. 3 - 10 addr yyyy in these eight clock cycles make up the 32-bit memory address. yyyy is one nibble of the entire address. addresses are transferred most significant nibble first. 11 tar0 1111b in then float in this clock cycle, the master (ich) has driven the bus to all 1s and then floats the bus, prior to the next clock cycle. this is the first part of the bus ?turnaround cycle?. 12 tar1 1111b (float) float then out the lpc takes control of the bus during this cycle. during the next clock cycle, it will be driving ?sync data?. 13 - 14 wsync 0101b (wait) out the lpc outputs the value 0101, a wait-sync (wsync, a.k.a. ?short-sync?), for two clock cycles. this value indicates to the master (ich) that data is not yet available from the part. this number of wait- syncs is a function of the device?s access time. 15 rsync 0000b (ready) out during this clock cycle, the lpc will generate a ?ready-sync? (rsync) indicating that the least significant nibble of the least significant byte will be available during the next clock cycle. 16 data yyyy out yyyy is the least significant nibble of the least significant data byte. 17 data yyyy out yyyy is the most significant nibble of the least significant data byte. 18 tar0 1111b out then float the lpc flash memory drives lad0 - lad3 to 1111b to indicate a turnaround cycle. 19 tar1 1111b (float) float then in the lpc flash memory floats its outputs, the master (ich) takes control of lad3 - lad0.
9 at49ll040 3343a?flash?6/03 write: write operations consist of start, cyctype + dir, address, data, tar and sync fields as shown in figure 2 and described in table 6. write cycles: for write cycles, after the address is transferred, the master writes the low nibble, then the high nibble of data. after that the master drives a tar field to give ownership of the bus to the lpc. after the second clock of the tar phase, the tar- get device assumes the bus and begins driving sync values. a tar field to give control back to the master follows this. figure 2. lpc single-byte write waveforms note: 1. field contents are valid on the rising edge of the present clock cycle. maddr tar tar sync clk lframe lad[3:0] data start cyctype + dir 1234567891011121314151617 table 6. lpc write cycle clock cycle field name field contents (1) lad[3:0] lad[3:0] direction comments 1 start 0000b in lframe must be active (low) for the part to respond. only the last start field (before lframe transitioning high) should be recognized. the start field contents indicate an lpc memory write cycle. 2 cyctype + dir 011xb in cycle type: indicates the type of cycle. bits 3:2 must be 01 for a memory cycle. dir: bit 1 indicates the direction of the transfer (1 for write). bit 0 is reserved. 3 - 10 addr yyyy in these eight clock cycles make up the 32-bit memory address. yyyy is one nibble of the entire address. addresses are transferred most significant nibble first. 11 data yyyy in this field is the least significant nibble of the data byte. this data is either the data to be programmed into the flash memory or any valid flash command. 12 data yyyy in this field is the most significant nibble of the data byte. 13 tar0 1111b in then float in this clock cycle, the master (ich) has driven the bus to all 1s and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turnaround cycle?. 14 tar1 1111b (float) float then out the lpc takes control of the bus during this cycle. during the next clock cycle it will be driving the ?sync? data. 15 rsync 0000b out the lpc outputs the values 0000, indicating that it has received data or a flash command. 16 tar0 1111b out then float the lpc flash memory drives lad0 - lad3 to 1111b to indicate a turnaround cycle. 17 tar1 1111b (float) float then in the lpc flash memory floats its outputs, the master (ich) takes control of lad3 - lad0.
10 at49ll040 3343a?flash?6/03 output disable: when the lpc is not selected through a lpc read or write cycle, the lpc interface outputs (lad[3:0]) are disabled and will be placed in a high-imped- ance state. bus abort the bus abort operation can be used to immediately abort the current bus operation. a bus abort occurs when lframe is driven low, v il , during the bus operation; the mem- ory will tri-state the input/output communication pins, lad3 - lad0 and the lpc state machine will reset. during a write cycle, there is the possibility that an internal flash write or erase operation is in progress (or has just been initiated). if the lframe is asserted during this time frame, the inter nal operation will not abort. the internal lpc state machine will not initiate a flash write or erase operation until it has received the last nibble from the chipset. this means that lframe can be asserted as late as cycle 12 (table 6) and no internal flash operation will be attempted. hardware write-protect pins tbl and wp : two pins are available with the lpc to provide hardware write-protect capabilities. the top sector lock (tbl ) pin is a signal, when held low (active), prevents program or sector erase operations in the top sector of the device (10) where critical code can be stored. when tbl is high, hardware write protection of the top sector is disabled. the write-protect (wp ) pin serves the same function for all the remaining sectors except the top sector. wp operates independently from tbl and does not affect the lock status of the top sector. the tbl and wp pins must be set to the desired protection state prior to starting a pro- gram or erase operation since they are sampled at the beginning of the operation. changing the state of tbl or wp during a program or erase operation may cause unpredictable results. the new lock status will take place after the program or erase operation completes. these pins function in combination with the register-based sector locking (to be explained later). these pins, when active, will write-protect the appropriate sector(s), regardless of the associated sector locking registers. (for example, when tbl is active, writing to the top sector is prevented, regardless of the state of the write lock bit for the top sector?s locking register. in such a case, clearing the write-protect bit in the register will have no functional effect, even though the register may indicate that the sector is no longer locked. the register may still be set to read-lock the sector, if desired.) device memory map with lpc hardware lock architecture sector size (bytes) address range hardware write-protect pin sa10 32k 78000 - 7ffff tbl sa9 8k 76000 - 77fff wp sa8 8k 74000 - 75fff wp sa7 16k 70000 - 73fff wp sa6 64k 60000 - 6ffff wp sa5 64k 50000 - 5ffff wp sa4 64k 40000 - 4ffff wp sa3 64k 30000 - 3ffff wp sa2 64k 20000 - 2ffff wp sa1 64k 10000 - 1ffff wp sa0 64k 00000 - 0ffff wp
11 at49ll040 3343a?flash?6/03 register-based locking and general- purpose input registers a series of registers are available in the lpc to provide software read and write locking and gpi feedback. these registers are accessible through standard addressable mem- ory space. registers: the at49ll040 has two types of registers: sector-locking registers and general-purpose input registers. the two types of registers appear at their respective address locations in the 4 gb system memory map. sector-locking registers: the at49ll040 has 11 (lr0 - lr10) sector-locking registers. each sector-locking register controls the lock protection for a sector of mem- ory as shown in table 7. the sector-locking registers are accessible through the register memory address shown in the third column of table 7. the sector-locking registers are read/write as shown in the last column of table 7. each sector has three dedicated lock- ing bits as shown in table 8 and table 9. table 7. sector-locking registers for at49ll040 register name sector size register memory address (id [3:0] = 0000) default value type lr10 32k ff7f8002h 01h r/w lr9 8k ff7f6002h 01h r/w lr8 8k ff7f4002h 01h r/w lr7 16k ff7f0002h 01h r/w lr6 64k ff7e0002h 01h r/w lr5 64k ff7d0002h 01h r/w lr4 64k ff7c0002h 01h r/w lr3 64k ff7b0002h 01h r/w lr2 64k ff7a0002h 01h r/w lr1 64k ff790002h 01h r/w lr0 64k ff780002h 01h r/w fgpi-reg ff7c0100h n/a ro table 8. function of sector-locking bits bit function 7:3 reserved 2 read lock 1 = prevents read operations in the sector where set. 0 = normal operation for reads in the sector where clear. this is the default state. 1 lock-down 1 = prevents further set or clear operations to the write lock and read lock bits. lock-down can only be set, but not cleared. the sector will remain locked-down until reset (with rst or init ), or until the device is power-cycled. 0 = normal operation for write lock and read lock bits altering in the sector where clear. this is the default state. 0 write lock 1 = prevents program or erase operations in the sector where set. this is the default state. 0 = normal operation for programming and erase in the sector where clear.
12 at49ll040 3343a?flash?6/03 note: 1. the write lock bit must be set to the desired protection state prior to starting a program or erase operation since it i s sam- pled at the beginning of the operation. changing the state of the write lock bit during a program or erase operation may cause unpredictable results. the new lock status will take place after the program or erase operation completes. the individ- ual bit functions are described in the following sections. read lock: the default read status of all sectors upon power-up is read-unlocked. when a sector?s read-lock bit is set (1 state), data cannot be read from that sector. an attempted read from a read-locked sector will result in data 00h being read. (note that failure is not reflected in the status regi ster). the read-lock status can be unlocked by clearing (0 state) the read-lock bit, provided the lock-down bit has not been set. the cur- rent read-lock status of a particular sector can be determined by reading the corresponding read-lock bit. write lock: the default write status of all sectors upon power-up is write-locked (1 state). any program or eras e operations attempted on a locked sector will return an error in the status register (indicating sector lock). the status of the locked sector can be changed to unlocked (0 state) by clearing the write-lock bit, provided the lock-down bit is not also set. the current write-lock status of a particular sector can be determined by reading the corresponding write-lock bit. any program or erase operations attempted on a locked sector will return an error in the st atus register (indicating sector lock). the write-lock functions in conjunction with the hardware write-lock pins, tbl and wp . when active, these pins take precedence ov er the register-locking function and write- lock the top sector or remaining sectors, respectively. reading this register will not read the state of the tbl or wp pins. lock-down: when in the lpc interface mode, the default lock-down status of all sec- tors upon power-up is not-locked-down (0 state). the lock-down bit for any sector may be set (1 state), but only once, as future attempted changes to that sector locking regis- ter will be ignored. the lock-down bit is only cleared upon a device reset with rst or init . the current lock-down status of a particular sector can be determined by reading the corresponding lock-down bit. once a sector?s lock-down bit is set, the read- and write-lock bits for that sector can no longer be modified and the sector is locked down in its current state of read and write accessibility. general-purpose inputs register: this register reads the status of the gpi[4:0] pins on the lpc at power-up. since this is a pass-through register, there is no default value as shown in table 7. it is recommended that the gpi pins be in the desired state before lframe is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. table 9. register-based locking value definitions data reserved data 7 - 3 read lock, data 2 lock-down, data 1 write lock, data 0 resulting sector state (1) 00 00000 000 full access 01 00000 001 write locked ? default state at power-up 02 00000 010 locked open (full access locked down) 03 00000 011 write locked down 04 00000 100 read locked 05 00000 101 read and write locked 06 00000 110 read locked down 07 00000 111 read and write locked down
13 at49ll040 3343a?flash?6/03 notes: 1. x = any valid address within the device. 2. the sector must be not be write locked when attempting sector erase or program operations. attempts to issue a sector erase or byte program to a write locked sector will fail. 3. sa = sector address. any byte address within a sector can be used to designate the sector address (see page 10). 4. if a main sector erase command is given to a parametric/boot sector, the entire 64k region sa10 - sa7 will be erased. 5. either 40h or 10h is recognized as the program setup. 6. following the product id entry command, read operations access manufacture and device id. see table 11. 7. aid = address used to read data for manufacture or device id. 8. srd = data read from status register. table 10. general-purpose input registers bit function 7:5 reserved 4 gpi[4] reads status of general-purpose input pin (plcc-30/tsop-7) 3 gpi[3] reads status of general-purpose input pin (plcc-3/tsop-15) 2 gpi[2] reads status of general-purpose input pin (plcc-4/tsop-16) 1 gpi[1] reads status of general-purpose input pin (plcc-5/tsop-17) 0 gpi[0] reads status of general-purpose input pin (plcc-6/tsop-18) command definitions in (hex) command sequence bus cycles operation 1st bus cycle operation 2nd bus cycle addr data addr data read array/reset 1 write xxxx ff main sector erase (64-kbyte sector) (2)(3) 2writesa20writesad0 parametric/boot sector erase (32-/16-/8-kbyte sector) (2)(3)(4) 2writesa21writesad0 byte program (2)(5) 2 write addr 40 or 10 write addr d in product id entry (6) 2 write xxxx 90 read aid (7) d out read status register 2 write xxxx 70 read xxxx srd (8) clear status register 1 write xxxx 50
14 at49ll040 3343a?flash?6/03 read array: upon initial device power-up and after exit from reset, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal state machine (wsm) has started a block erase or program operation, the device will not recognize the read array command until the operation is completed. the read array command functions independently of the v pp voltage. product identification: the product identification mode identifies the device and manufacturer as atmel. following the product id entry command, read cycles from the addresses shown in table 11 retrieve the manufacturer and devic e code. to exit the product identification mode, any valid command can be written to the device. the product id entry command functions independently of the v pp voltage. sector erase: before a byte can be programmed, it must be erased. the erased state of the memory bits is a logical ?1?. since the at49ll040 does not offer a complete chip erase, the device is organized into multiple sectors that can be individually erased. the device incorporates two erase commands that allow either a main sector (64k bytes) to be erased or allow a parametric/boot sector (32k/16k/8k bytes) to be erased. the sector erase command is a two-bus cycle operation. the sector whose address is valid at the second falling edge of the we will be erased, provided the given sector is not protected. successful sector erase requires that the corresponding sector?s write lock bit be cleared and the corresponding write-protect pin (tbl or wp ) be inactive. if sector erase is attempted when the sector is locked, the sector erase will fail, with the reason for fail- ure in the status register. byte programming: the device is programmed on a byte-by-byte basis. program- ming is accomplished via the internal devic e command register and is a two-bus cycle operation. the programming address and data are latched in the second bus cycle. the device will automatically generate the requ ired internal progr amming pulses. please note that a ?0? cannot be programmed back to a ?1?; only an erase operation can convert ?0?s to ?1?s. after the program command is written, the device automatically outputs the status regis- ter data when read. when programming is complete, the status register may be checked. if a program error is detected, the status register should be cleared before cor- rective action is taken by the software. the internal wsm verification error checking only detects ?1?s that do not successfully program to ?0?s. a successful program operation also requires that the corresponding sector?s write lock bit be cleared, and the corresponding write-protect pin (tbl or wp ) be inactive. if a pro- gram operation is attempted when the sector is locked, the operation will fail. table 11. identifier codes code address (aid) data manufacturer code 00000 1fh device code 00001 eah
15 at49ll040 3343a?flash?6/03 read status register: the status register may be read to determine when a sec- tor erase or program completes and whether the operation completed successfully. the status register may be read at any time by writing the read status register command. after writing this command, all subsequent read operations will return data from the sta- tus register until another valid command is written. the read status register command functions independently of the v pp voltage. clear status register: error flags in the status register can only be set to ?1?s by the wsm and can only be reset by the clear status register command. these bits indi- cate various failure conditions. the cl ear status register command functions independently of the applied v pp voltage. notes: 1. check b7 to determine sector erase or program completion. b6 - b0 are invalid while b7 = ?0?. 2. if both b5 and b4 are ?1?s after a sector erase attempt, an improper command sequence was entered. 3. b1 does not provide a continuous indication of write lock bit, tbl pin or wp pin val- ues. the wsm interrogates the write lock bit, tbl pin or wp pin only after a sector erase or program operation. depending on the attempted operation, it informs the system whether or not the selected sector is locked. 4. b0 is reserved for future use and should be masked out when polling the status register. 5. b2 = b6 = 0. a/a mux interface the following information applies only to the at49ll040 when in a/a mux mode. infor- mation on lpc mode (the standard operating mode) is detailed earlier in this document. electrical characteristics in a/a mux mode are provided on pages starting from page 22. the at49ll040 is designed to offer a parallel programming mode for faster factory pro- gramming. this mode, called a/a mux mode, is selected by having this ic pin high. the ic pin is pulled down internally in the at49ll040, so a modest current should be expected to be drawn (see table 1 on page 3 for further information). four control pins dictate data flow in and out of the component: r/c , oe , we , and rst . r/c is the a/a mux control pin used to latch row and column addresses. oe is the data output control pin (i/o0 - i/o7), drives the selected memory data onto the i/o bus, when active we and rst must be at v ih . bus operation: all a/a mux bus cycles can be conformed to operate on most auto- mated test equipment and prom programmers. status register definition b7 write state machine status (1) 1 ready 0busy b5 erase status (2) 1 error in sector erasure 0 successful sector erase b4 program status 1 error in program 0 successful program b1 device protect status (3) 1 write lock bit, tbl pin or wp pin detected, operation abort 0 unlock b0 reserved for future enhancements (4)
16 at49ll040 3343a?flash?6/03 notes: 1. x can be v il or v ih for control and address input pins and v pph1 for the vpp supply pin. see the ?dc characteristics? for v pph1 voltages. 2. see table 11 on page 14 for product id entry data and addresses. 3. command writes involving sector erase or program are reliably executed when v pp = v pph1 and v cc = v cc 0.3v. 4. refer to ?a/a mux read-only operations? for valid d in during a write operation. 5. v ih and v il refer to the dc characteristics associated with flash memory output buff- ers: v il min = 0.5v, v il max = 0.8v, v ih min = 2.0v, v ih max = v cc + 0.5v. output disable/enable: with oe at a logic-high level (v ih ), the device outputs are disabled. output pins i/o0 - i/o7 are placed in the high-impedance state. with oe at a logic-low level (v il ), the device outputs are enabled. output pins i/o0 - i/o7 are placed in a output-drive state. row/column addresses: r/c is the a/a mux control pin used to latch row (a0 - a10) and column addresses (a11 - a18). r/c latches row addresses on the falling edge and column addresses on the rising edge. rdy/busy : an open drain ready/busy output pin provides a hardware method of detecting the end of a program or erase operation. rdy/busy is actively pulled low dur- ing the internal program and erase cycles and is released at the completion of the cycle. bus operations mode rst oe we address v pp i/o0 - i/o7 read (1)(5) v ih v il v ih xxd out output disable (5) v ih v ih v ih x x high-z product id entry (5) v ih v il v ih (2) xnote 3 write (3)(4)(5) v ih v ih v il xx d in
17 at49ll040 3343a?flash?6/03 notes: 1. all specified voltages are with respect to gnd. minimum dc voltage on the v pp pin is -0.5v. during transitions, this level may undershoot to -2.0v for periods of <20 ns. during transitions, this level may overshoot to v cc + 2.0v for periods <20 ns. 2. do not violate processor or chipset limitations on the init pin. note: 1. this temperature requirement is different from the normal commercial operating condition of flash memories. notes: 1. input leakage currents include high-z output leakage for all bi-directional buffers with tri-state outputs. 2. refer to pci spec. 3. inputs are not ?5-volt safe.? 4. i il may be changed on ic and id pins (up to 200 a) if pulled against internal pull-downs. refer to the pin descriptions. 5. do not violate processor or chipset specifications regarding the init pin voltage. absolute maximum ratings* voltage on any pin ....... ...................-0.5v to +vcc + 0.5v (1)(2) *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating conditions temperature and v cc symbol parameter test condition min max unit t c operating temperature (1) case temperature 0 +85 c v cc v cc supply voltage 3.0 3.6 v lpc interface dc input/ou tput specifications symbol parameter conditions min max units v ih (3) input high voltage 0.5 v cc v cc + 0.5 v v ih (init ) (5) init input high voltage 1.35 v cc + 0.5 v v il (init ) (5) init input low voltage 0.85 v v il (3) input low voltage -0.5 0.3 v cc v i il (4) input leakage current (1) 0 < v in < v cc 10 a v oh output high voltage i out = -500 a 0.9 v cc v v ol output low voltage i out = 1500 a 0.1 v cc v c in input pin capacitance 13 pf c clk clk pin capacitance 3 12 pf l pin(2) recommended pin inductance 20 nh
18 at49ll040 3343a?flash?6/03 notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all packages. 2. v pp = v cc . 3. v ih = 0.9 v cc , v il = 0.1 v cc per the pci output v oh and v ol spec. 4. this number is the worst case of i pp + i cc memory core + i cc lpc interface. power supply specifications ? all interfaces symbol parameter conditions min max units v pph1 v pp voltage 0 3.6 v v pplk v pp lockout voltage 1.5 v v lko v cc lockout voltage 1.5 v i ccsl1 v cc standby current (lpc interface) (2) voltage range of all inputs is v ih to v il , lframe = v ih , (3) v cc = 3.6v, clk f = 33 mhz no internal operations in progress 100 (4) a i ccsl2 v cc standby current (lpc interface) (2) lframe = v il (3) v cc = 3.6v, clk f = 33 mhz no internal operations in progress 10 (4) ma i cca v cc active current (2) v cc = v cc max, (3) clk f = 33 mhz any internal operation in progress, i out = 0 ma 67 (4) ma i ppr v pp read current (2) v pp v cc 200 a i ppwe v pp program or erase current v pp = 3.0 - 3.6v (2) 40 ma
19 at49ll040 3343a?flash?6/03 notes: 1. pci specification output load is used. 2. i oh = (98.0/v cc ) * (v out - v cc ) *(v out + 0.4 v cc ). 3. i ol = (256/v cc ) * v out (v cc - v out ). lpc interface ac timing specifications notes: 1. pci components must work with any clock frequency between nominal dc and 33 mhz. frequencies less than16 mhz may be guaranteed by design rather than testing. 2. applies only to rising edge of signal. clock waveform lpc interface ac input /output specifications symbol parameter condition min max units i oh (ac) switching current high 0 < v out 0.3 v cc -12 v cc ma 0.3 v cc < v out <0.9 v cc -17.1 (v cc - v out )ma 0.7 v cc < v out < v cc note 2 (test point) v out = 0.7 v cc -32 v cc ma i ol (ac) switching current low v cc > v out 0.6 v cc 16 v cc ma 0.6 v cc > v out > 0.1 v cc -17.1 (v cc - v out )ma 0.18 v cc > v out > 0 note 3 (test point) v out = 0.18 v cc 38 v cc ma i cl low clamp current -3 < v in -1 -25 + (v in + 1)/0.015 ma i ch high clamp current v cc + 4 > v in v cc + 1 25 + (v in - v cc - 1)/0.015 ma slewr output rise slew rate 0.2 v cc - 0.6 v cc load (1) 14v/ns slewf output fall slew rate 0.6 v cc - 0.2 v cc load (1) 14v/ns clock specification symbol parameter condition min max units t cyc clk cycle time (1) 30 ns t high clk high time 11 ns t low clk low time 11 ns - clk slew rate peak-to-peak 1 4 v/ns -rst or init slew rate (2) 50 mv/ns t cyc t high t low 0.6 v cc 0.5 v cc 0.4 v cc 0.3 v cc 0.4 v cc, p-to-p (minimum) 0.2 v cc
20 at49ll040 3343a?flash?6/03 notes: 1. minimum and maximum times have different loads. see pci spec. 2. for purposes of active/float timing measurements, the high-z or ?off? state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. this parameter applies to any input type (excluding clk). output timing parameters input timing parameters signal timing parameters symbol pci symbol parameter min max units t chqx t val clk to data out (1) 211ns t chqx t on clk to active (float to active delay) (2) 2ns t chqz t off clk to inactive (active to float delay) (2) 28 ns t avch t dvch t su input set-up time (3) 7 ns t chax t chdx t h input hold time (3) 0 ns t vspl t rst reset active time after power stable 1 ms t cspl t rst-clk reset active time after clk stable 100 s t plqz t rst-off reset active to output float delay (2) 48 ns t off t on t val v th v tl v test clk lad[3:0] (valid output data) lad[3:0] (float output data) t h v th v tl v max v test clk lad[3:0] (valid input data) t su inputs valid
21 at49ll040 3343a?flash?6/03 note: 1. the input test environment is done with 0.1 v cc of overdrive over v ih and v il . timing parameters must be met with no more overdrive than this. v max specifies the maximum peak-to-peak waveform allowed for measuring the input timing. production testing may use different voltage values, but must correlate results back to these parameters. note: 1. a reset latency of 20 s will occur if a reset procedure is performed during a programming or erase operation. ac waveform for reset operation notes: 1. typical values measured at t a = +25 c and nominal voltages. 2. excludes system-level overhead. interface measurement condition parameters symbol value units v th (1) 0.6 v cc v v tl (1) 0.2 v cc v v test 0.4 v cc v v max (1) 0.4 v cc v input signal edge rate 1 v/ns reset operations symbol parameter min max unit t plph (1) rst or init pulse low time (if rst or init is tied to v cc , this specification is not applicable) 100 ns sector programming times parameter 3.3v v pp unit typ (1) max byte program time (2) 30.0 300 s sector program time (2) 2.0 20.0 sec sector erase time (2) 0.8 1.0 sec v ih v il rst t plph
22 at49ll040 3343a?flash?6/03 electrical characteristics in a/a mux mode: certain specifications differ from the previous sections, when programming in a/a mux mode. the following subsec- tions provide this data. any information that is not shown here is not specific to a/a mux mode and uses the lpc mode specifications. notes: 1. input leakage currents include high-z output leakage for all bi-directional buffers with tri-state outputs. 2. refer to pci spec. 3. inputs are not ?5-volt safe.? 4. i il may be changed on ic and id pins (up to 200 a) if pulled against internal pull-downs. refer to the pin descriptions. notes: 1. if rst is asserted when the wsm is not busy (ry/by = 1), the reset will complete within 100 ns. 2. a reset time, t phav , is required from the latter of ry/by or rst going high until outputs are valid. ac waveforms for reset operations a/a mux mode interface dc input/output specifications symbol parameter conditions min max unit v ih (3) input high voltage 0.5 v cc v cc + 0.5 v v il (3) input low voltage -0.5 0.8 v i il (4) input leakage current v cc = v cc max, v out = v cc or gnd + 10 a v oh output high voltage v cc = v cc min, i oh = -2.5 ma v cc = v cc min, i oh = -100 a 0.85 v cc min v cc = 0.4 v v v ol output low voltage v cc = v cc min, i ol = 2 ma 0.4 v c in input pin capacitance 13 pf c clk clk pin capacitance 3 12 pf l pin (2) recommended pin inductance 20 nh reset operations symbol parameter min max unit t plph rst pulse low time (if rst is tied to v cc , this specification is not applicable.) 100 ns t plrh rst low to reset during sector erase or program (1)(2) 20 s v ih v il v ih v il t plph t plrh ry/by rst
23 at49ll040 3343a?flash?6/03 notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe may be delayed up to t chqv - t glqv after the rising edge of r/c without impact on t chqv . 3. t c = 0 c to +85 c, 3.3v 0.3v v cc . a/a mux read timing diagram a/a mux read-only operations (1)(2)(3) symbol parameter min max units t avav read cycle time 250 ns t avcl row address setup to r/c low 50 ns t clax row address hold from r/c low 50 ns t avch column address setup to r/c high 50 ns t chax column address hold from r/c high 50 ns t chqv r/c high to output delay (2) 150 ns t glqv oe low to output delay (2) 50 ns t phav rst high to row address setup 1 s t glqx oe low to output in low-z 0 ns t ghqz oe high to output in high-z 50 ns t qxgh output hold from oe high 0 ns v ih v il r/c v ih v il oe v ih v il we v ih v il rst v oh v ol i/o v ih v il addresses t glqx t chax t avch t clax t avcl t qxgh t ghqz t glqv t chqv t phav t avav row address stable next address stable data valid high-z high-z column address stable
24 at49ll040 3343a?flash?6/03 notes: 1. refer to ?a/a mux read-only operations? for valid a in and d in for sector erase or program, or other commands. 2. t c = 0 c to +85 c, 3.3v 0.3v v cc . a/a mux write timing diagram a/a mux write operations (1)(2) symbol parameter min max units t phwl rp high recovery to we low 1 s t wlwh write pulse width low 100 ns t dvwh data setup to we high (1) 50 ns t whdx data hold from we high (1) 8ns t avcl row address setup to r/c low (1) 50 ns t clax row address hold from r/c low (1) 50 ns t avch column address setup to r/c high (1) 50 ns t chax column address hold from r/c high (1) 50 ns t whwl write pulse width high 100 ns t chwh r/c high setup to we high 50 ns t vpwh v pp1 setup to we high 100 ns t whgl write recovery before read 150 ns t whrl we high to ry/by going low 0 ns t qvvl v pp1 hold from valid srd, ry/by high 0 ns v ih v il r/c v ih v il we v oh v ol i/o v ih v il ry/by v ih v il rst v pph1 v il v pp (v) v ih v il oe v ih v il addresses t qvvl t whrl t whdx t chwh t chax t clax t avch t avcl t whwl t wlwh t dvwh t vpwh t t whgl t phwl r1 c1 r2 c2 valid srd d in d in ab c d e f ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes a=v cc power-up and standby b = write sector erase or program setup c = write sector erase confirm or valid address and data d = automated erase or program delay e = read status register data f = ready to write another command
25 at49ll040 3343a?flash?6/03 at49ll040 ordering information i cc (ma) ordering code package operation range active standby 67 0.10 AT49LL040-33JC at49ll040-33tc 32j 40t extended commercial (0 to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier package (plcc) 40t 40-lead, plastic thin small outline package, type i (tsop)
26 at49ll040 3343a?flash?6/03 packaging information 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
27 at49ll040 3343a?flash?6/03 40t ? tsop, type i 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40t , 40-lead (10 x 20 mm package) plastic thin small outline package, type i (tsop) b 40t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation cd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 9.90 10.00 10.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
printed on recycled paper. 3343a?flash?6/03 /xm disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products , expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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